ATMEGA128-16MC Atmel, ATMEGA128-16MC Datasheet - Page 90

• Manufacturer Part Number: ATMEGA128-16MC
• Description: IC AVR MCU 128K 16MHZ COM 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

External Interrupt
Control Register B –
EICRB
90
ATmega128
Table 48. Interrupt Sense Control
Note:
Table 49. Asynchronous External Interrupt Characteristics
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is
enabled. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low.
Table 50. Interrupt Sense Control
Note:
Bit
Read/Write
Initial Value
ISCn1
Symbol
ISCn1
t
0
0
1
1
0
0
1
1
INT
1. n = 3, 2, 1or 0.
1. n = 7, 6, 5 or 4.
ISCn0
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Parameter
Minimum pulse width for
asynchronous external interrupt
0
1
0
1
0
1
0
1
ISC71
R/W
7
0
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt
request.
The rising edge between two samples of INTn generates an interrupt
request.
Description
The low level of INTn generates an interrupt request.
Reserved
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
ISC70
R/W
6
0
ISC61
R/W
5
0
(1)
(1)
Table
ISC60
R/W
4
0
50. The value on the INT7:4 pins are sampled before
ISC51
R/W
Condition
3
0
ISC50
R/W
2
0
Min
ISC41
R/W
1
0
Typ
50
ISC40
R/W
0
0
Max
EICRB
Units
2467V–AVR–02/11
ns