AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 526
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
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Part Number:
AT32UC3B0512-A2UT
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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32059I–06/2010
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the CDTYx
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the CMRx register. By default the signal starts by
a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in the
CALG field of the CMRx register. The default mode is left aligned.
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
X CPRD
CRPD
2
2
duty cycle
×
×
×
duty cycle
MCK
X CPRD
CPRD DIVA
MCK
MCK
×
MCK
×
DIVA
)
×
=
)
)
=
or
(
------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
(
---------------------------------------------------------------------------------------------------------------------- -
)
(
period 2 ⁄
(
--------------------------------------------- -
or
CRPD
(
--------------------------------------------------- -
2 CPRD
–
MCK
×
×
DIVAB
⁄
) 1 fchannel_x_clock
MCK
–
×
period
⁄
(
)
DIVB
period 2 ⁄
)
)
×
CDTY
×
CDTY
)
) )
AT32UC3B
526
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