AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 434
![IC MCU AVR32 512K FLASH 64TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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22.8.2.8
Register Name:
Access Type:
Offset:
Reset Value:
•
•
32059I–06/2010
EPRSTn: Endpoint n Reset
EPENn: Endpoint n Enable
31
23
15
7
-
-
-
-
Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and start using the FIFO.
This bit is cleared upon receiving a USB reset.
1: The endpoint n is enabled.
0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint
reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint
configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).
n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
Endpoint Enable/Reset Register
EPRST6
EPEN6
30
22
14
6
-
-
UERST
Read/Write
0x001C
0x00000000
EPRST5
EPEN5
29
21
13
5
-
-
EPRST4
EPEN4
28
20
12
4
-
-
EPRST3
EPEN3
27
19
11
3
-
-
EPRST2
EPEN2
26
18
10
2
-
-
EPRST1
EPEN1
25
17
9
1
-
-
AT32UC3B
EPRST0
EPEN0
24
16
8
0
-
-
434
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