AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 269
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Figure 20-8. Transmitter Block Diagram
20.7.3
32059I–06/2010
Transmitter Clock
RX_FRAME_SYNC
Receiver Operations
TX_FRAME_SYNC
TFMR.DATLEN
TCMR.STTDLY
TFMR.FSDEN
Selector
Start
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by writing to the RCMR register. See
The frame synchronization is configured by writing to the Receive Frame Mode Register
(RFMR). See
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR register. The data is transferred from the shift register depending on the
data format selected.
When the receiver shift register is full, the SSC transfers this data in the Receive Holding Regis-
ter (RHR), the Receive Ready bit is set in the SR register (SR.RXREADY) and the data can be
read in the RHR register. If another transfer occurs before a read of the RHR
Receive Overrun bit is set in the SR register (SR.OVRUN) and the receiver shift register is trans-
ferred to the RHR register.
TFMR.MSBF
THR
Transmit Shift Register
Section
TFMR.DATDEF
0
20.7.5.
1
TSHR
0
1
TFMR.FSLEN
TCMR.STTDLY
TFMR.DATNB
TFMR.FSDEN
CR.TXEN
CR.TXDIS
SR.TXEN
Section
20.7.4.
AT32UC3B
TX_DATA
register
, the
269
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