AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 40
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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9.5.5.1
9.5.5.2
32059I–06/2010
PLL0 clock
Osc0 clock
Slow clock
Selecting PLL or oscillator for the main clock
Selecting synchronous clock division ratio
MCSEL
any tapping of this prescaler, or the undivided main clock, as long as f
nous clock source can be changed on-the fly, responding to varying load in the application. The
clock domains can be shut down in sleep mode, as described in
Additionally, the clocks for each module in the four domains can be individually masked, to avoid
power consumption in inactive modules.
Figure 9-4.
The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default,
the main clock will be connected to the slow clock. The user can connect the main clock to Oscil-
lator 0 or PLL0 by writing the MCSEL bitfield in the Main Clock Control Register (MCCTRL). This
must only be done after that unit has been enabled, otherwise a deadlock will occur. Care
should also be taken that the new frequency of the synchronous clocks does not exceed the
maximum frequency for each clock domain.
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling
value, resulting in a CPU clock frequency:
f
CPU
Prescaler
= f
instruction
main
Synchronous clock generation
Sleep
/ 2
(CPUSEL+1)
CPUSEL
CPUDIV
0
1
Controller
Main clock
Sleep
CPUMASK
Mask
”Sleep modes” on page
CPU
AT32UC3B
f
PBA,B,
CPU clocks
HSB clocks
PBB clocks
PBAclocks
. The synchro-
42.
40
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