AT32UC3A364S-CTUR Atmel, AT32UC3A364S-CTUR Datasheet - Page 42

• Manufacturer Part Number: AT32UC3A364S-CTUR
• Description: IC MCU 64KB FLASH 144TFBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364S-CTUR

• Package / Case: 144-TBGA
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 66MHz
• Number Of I /o: 110
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.24
8.4.25
8.4.26
8.4.27
32072AS–AVR32–03/09
Advanced Encryption Standart
Audio Bitstream DAC
On-Chip Debug
JTAG and Boundary Scan
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Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
128-bit/192-bit/256-bit cryptographic key
12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit
cryptographic key
Support of the five standard modes of operation specified in the NIST Special Publication 800-
38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques:
8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode
Last output data mode allows optimized Message Authentication Code (MAC) generation
Hardware counter measures against differential power analysis attacks
Connection to DMA Controller capabilities optimizes data transfers for all operating modes
Digital Stereo DAC
Oversampled D/A conversion architecture
Digital bitstream outputs
Parallel interface
Connected to DMA Controller for background transfer without CPU intervention
Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
JTAG access to all on-chip debug functions
Advanced program, data, ownership, and watchpoint trace supported
NanoTrace JTAG-based trace access
Auxiliary port for high-speed trace information
Hardware support for 6 program and 2 data breakpoints
Unlimited number of software breakpoints supported
Automatic CRC check of memory regions
IEEE1149.1 compliant JTAG Interface
Boundary-Scan Chain for board-level testing
Direct memory access and programming capabilities through JTAG interface
On-Chip Debug access in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0)
– Electronic Code Book (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
– Counter (CTR)
– Oversampling ratio fixed 128x
– FIR equalization filter
– Digital interpolation filter: Comb4
– 3rd Order Sigma-Delta D/A converters
AT32UC3A3
42