AT32UC3A364S-CTUR Atmel, AT32UC3A364S-CTUR Datasheet - Page 35

• Manufacturer Part Number: AT32UC3A364S-CTUR
• Description: IC MCU 64KB FLASH 144TFBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364S-CTUR

• Package / Case: 144-TBGA
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 66MHz
• Number Of I /o: 110
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.5
8.4.6
8.4.7
32072AS–AVR32–03/09
External Interrupts Controller
Flash Controller
HSB Bus Matrix
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Up to 64 groups of interrupts with up to 32 interrupt requests in each
Dedicated interrupt request for each interrupt
Individually maskable interrupts
Interrupt on rising or falling edge
Interrupt on high or low level
Asynchronous interrupts for sleep modes without clock
Filtering of interrupt lines
Maskable NMI interrupt
Keypad scan support
Controls flash block with dual read ports allowing staggered reads.
Supports 0 and 1 wait state bus access.
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
32-bit HSB interface for reads from flash array and writes to page buffer.
32-bit PB interface for issuing commands to and configuration of the controller.
16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16)
pages.
Regions can be individually protected or unprotected.
Additional protection of the Boot Loader pages.
Supports reads and writes of general-purpose NVM bits.
Supports reads and writes of additional NVM pages.
Supports device protection through a security bit.
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
Interface to Power Manager for power-down of flash-blocks in sleep mode.
User Interface on peripheral bus
Configurable Number of Masters (Up to sixteen)
Configurable Number of Slaves (Up to sixteen)
One Decoder for Each Master
Three Different Memory Mappings for Each Master (Internal and External boot, Remap)
One Remap Function for Each Master
Programmable Arbitration for Each Slave
Programmable Default Master for Each Slave
– Round-Robin
– Fixed Priority
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
AT32UC3A3
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