AT32UC3A364S-CTUR Atmel, AT32UC3A364S-CTUR Datasheet - Page 36

• Manufacturer Part Number: AT32UC3A364S-CTUR
• Description: IC MCU 64KB FLASH 144TFBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364S-CTUR

• Package / Case: 144-TBGA
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 66MHz
• Number Of I /o: 110
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.8
8.4.9
8.4.10
32072AS–AVR32–03/09
External Bus Interface
Static Memory Controller
SDRAM Controller
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One Cycle Latency for the First Access of a Burst
Zero Cycle Latency for Default Master
One Special Function Register for Each Slave (Not dedicated)
Optimized for application memory space support
Integrates three external memory controllers:
Additional logic for NAND Flash/SmartMedia
Optimized external bus:16-bit data bus
Up to 6 Chip Selects, Configurable Assignment:
6 chip selects available
64-Mbytes address space per chip select
8- or 16-bit data bus
Word, halfword, byte transfers
Byte write or byte select lines
Programmable setup, pulse and hold time for read signals per chip select
Programmable setup, pulse and hold time for write signals per chip select
Programmable data float time per chip select
Compliant with LCD module
External wait request
Automatic switch to slow clock mode
Asynchronous read in page mode supported: page size ranges from 4 to 32 bytes
128-Mbytes address space
Numerous configurations supported
Programming facilities
– Static Memory Controller (SMC)
– SDRAM Controller (SDRAMC)
– Error Corrected Code (ECCHRS) controller
– NAND Flash support: 8-bit as well as 16-bit devices are supported
– CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are
– Up to 24-bit Address Bus, Up to 8-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on external memories
– Static Memory Controller on Chip Select 0
– SDRAM Controller or Static Memory Controller on Chip Select 1
– Static Memory Controller on Chip Select 2, Optional NAND Flash support
– Static Memory Controller on Chip Select 3, Optional NAND Flash support
– Static Memory Controller on Chip Select 4, Optional CompactFlash
– Static Memory Controller on Chip Select 5, Optional CompactFlash
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit data path
– Word, halfword, byte access
– Automatic page break when memory boundary has been reached
– Multibank ping-pong access
supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode)
are not handled.
TM
and CompactFlash
TM
support
TM
TM
AT32UC3A3
support
support
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