AT32UC3A364S-CTUR Atmel, AT32UC3A364S-CTUR Datasheet - Page 25
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AT32UC3A364S-CTUR
Manufacturer Part Number
AT32UC3A364S-CTUR
Description
IC MCU 64KB FLASH 144TFBGA
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3A364-CTUR.pdf
(75 pages)
Specifications of AT32UC3A364S-CTUR
Package / Case
144-TBGA
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
66MHz
Number Of I /o
110
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Core Size
32-Bit
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, I2S, JTAG, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Operating Supply Voltage
- 0.3 V to + 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
7. Memories
7.1
7.2
32072AS–AVR32–03/09
Embedded Memories
Physical Memory Map
•
•
The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot.
Note that AVR32UC CPU uses unsegmented translation, as described in the AVR32 Architec-
ture Manual.
The 32-bit physical address space is mapped as follows:
Table 7-1.
Device
Embedded CPU SRAM
Embedded Flash
EBI SRAM CS0
EBI SRAM CS2
EBI SRAM CS3
EBI SRAM CS4
EBI SRAM CS5
EBI SRAM CS1 /SDRAM CS0
USB Data
Embedded System SRAM 0
Internal High-Speed Flash
Internal High-Speed SRAM
– 256KBytes (AT32UC3A3256/S)
– 128Kbytes (AT32UC3A3128/S)
– 64Kbytes (AT32UC3A364/S)
– 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the
– 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix
High Speed Bud (HSB) matrix
• 0 wait state access at up to 36MHz in worst case conditions
• 1 wait state access at up to 66MHz in <orst case conditions
• Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding
• Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, Bootloader protection, Security Bit
• 32 fuses, preserved during Chip Erase
• User page for data to be preserved during Chip Erase
penalty of 1 wait state access
to only 15% compared to 0 wait state operation
AT32UC3A3 Physical Memory Map
0xD0000000
Start
Address
0x00000000
0x80000000
0xC0000000
0xC8000000
0xCC000000
0xD8000000
0xDC000000
0xE0000000
0xFF000000
Size
AT32UC3A325
6
64KByte
256KByte
16MByte
16MByte
16MByte
16MByte
16MByte
128MByte
64KByte
32KByte
Size
AT32UC3A312
8
64KByte
128KByte
16MByte
16MByte
16MByte
16MByte
16MByte
128MByte
64KByte
32KByte
AT32UC3A3
Size
AT32UC3A36
4
64KByte
64KByte
16MByte
16MByte
16MByte
16MByte
16MByte
128MByte
64KByte
32KByte
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