AT90USB1287-MUR Atmel, AT90USB1287-MUR Datasheet - Page 296

• Manufacturer Part Number: AT90USB1287-MUR
• Description: MCU AVR 128K FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90USBx
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.14.1
23.15 Interrupt system
296
AT90USB64/128
CRC Error (isochronous only)
Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers an inter-
rupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the
RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current
bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the
next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the
status of the new bank.
A CRC error can occur during IN stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI
interrupt from being triggered.
Example with 1 IN data bank
Example with 2 IN data banks
RXIN
FIFOCON
RXIN
FIFOCON
IN
IN
(to bank 0)
(to bank 0)
DATA
DATA
HW
HW
ACK
ACK
SW
SW
read data from CPU
read data from CPU
IN
BANK 0
BANK 0
(to bank 1)
DATA
SW
SW
IN
HW
ACK
(to bank 0)
read data from CPU
SW
DATA
BANK 1
HW
ACK
SW
read data from CPU
BANK 0
7593K–AVR–11/09