ATMEGA64-16AUR Atmel, ATMEGA64-16AUR Datasheet - Page 256

• Manufacturer Part Number: ATMEGA64-16AUR
• Description: MCU AVR 64KB FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset Register
Boundary-scan Chain
Boundary-scan
Specific JTAG
Instructions
EXTEST; 0x0
2490Q–AVR–06/10
The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states port
pins when reset, the Reset Register can also replace the function of the unimplemented optional
JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the External Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the Fuse set-
tings for the clock options, the part will remain reset for a Reset Time-out Period (refer to
Sources” on page
latched, so the reset will take place immediately, as shown in
Figure 126. Reset Register
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
Off-chip connections.
See
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG
instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not
implemented, but all outputs with tri-state capability can be set in high-impedant state by using
the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which data register is selected as path between TDI and TDO for each instruction.
Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For analog circuits having Off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The con-
tents of the latched outputs of the Boundary-scan Chain is driven out as soon as the JTAG IR-
Register is loaded with the EXTEST instruction.
The active states are:
•
•
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The internal scan chain is shifted by the TCK input.
“Boundary-scan Chain” on page 258
From Other Internal and
External Reset Sources
38) after releasing the Reset Register. The output from this data register is not
From
ClockDR · AVR_RESET
TDI
for a complete description.
D
Q
TDO
To
Figure
126.
ATmega64(L)
Internal Reset
“Clock
256