DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet - Page 19
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DSPIC30F2020-30I/MM
Manufacturer Part Number
DSPIC30F2020-30I/MM
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-30I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
15MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
135
35.3.3.4
Figure 35-13: SPI Slave, Frame Master Connection Diagram
35.3.3.5
Figure 35-14: SPI Slave, Frame Slave Connection Diagram
© 2008 Microchip Technology Inc.
SPI Slave, Frame Master Mode
SPI Slave, Frame Slave Mode
(SPI1 Slave, Framed Master)
(SPI1 Slave, Framed Slave)
Section 35. Serial Peripheral Interface (SPI) (Part II)
In the SPI Slave/Frame Master mode, the module acts as the SPI slave and takes its clock from
the other SPI module; however, it produces frame synchronization signals to control data
transmission (Figure 35-13). This mode is enabled by setting the MSTEN bit to ‘0’, the FRMEN
bit to ‘1’ and the SPIFSD bit to ‘0’.
The input SPI clock will be continuous in Slave mode. The SS1 pin will be an output when the
SPIFSD bit is low. Therefore, when the SPI1BUF is written, the module drives the SS1 pin to the
active state on the appropriate transmit edge of the SPI clock for one SPI clock cycle. Data will
start transmitting on the appropriate SPI clock transmit edge.
In the SPI Slave/Frame Slave mode, the module obtains both its clock and frame synchronization
signal from the Master module (Figure 35-14). This mode is enabled by setting MSTEN to ‘0’,
FRMEN to ‘1’ and SPIFSD to ‘1’.
In this mode, both the SCK1 and SS1 pins will be inputs. The SS1 pin is sampled on the sample
edge of the SPI clock. When SS1 is sampled at its active state, data will be transmitted on the
appropriate transmit edge of SCK1.
dsPIC30F
dsPIC30F
SDO1
SCK1
SDO1
SCK1
SDI1
SDI1
SS1
SS1
Frame Synchronization
Pulse
Frame Synchronization
Pulse
Serial Clock
Serial Clock
SDI1
SDO1
SCK1
SS1
SDI1
SDO1
SCK1
SS1
PROCESSOR 2
PROCESSOR 2
DS70272B-page 35-19
35