ATMEGA649P-AU Atmel, ATMEGA649P-AU Datasheet - Page 61
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA649P-AU
Manufacturer Part Number
ATMEGA649P-AU
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number:
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12. External Interrupts
12.1
8284A–AVR–10/10
Overview
The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins
that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as
outputs. This feature provides a way of generating a software interrupt. The pin change interrupt
PCI1 will trigger if any enabled PCINT15:8 pin toggles. Pin change interrupts PCI0 will trigger if
any enabled PCINT7:0 pin toggles. The PCMSK3
isters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT30:0 are detected asynchronously. This implies that these interrupts can be used for wak-
ing the part also from sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the
When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger
as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0
requires the presence of an I/O clock, described in
page
can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is
halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
Notes:
”System Clock and Clock Options” on page
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
30. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt
1. PCMSK3 and PCMSK2 are only present in ATmega3290A/3290PA/6490A/6490P.
2. PCINT30:16 are only present in ATmega3290A/3290PA/6490A/6490P. Only PCINT15:0 are
present in ATmega169A/169PA; ATmega329A/329PA and ATmega649A/649P. See
figurations” on page 2
and
”Register Description” on page 62
”EICRA – External Interrupt Control Register A” on page
30.
(1)
, PCMSK2
”Clock Systems and their Distribution” on
(1)
, PCMSK1, and PCMSK0 Reg-
for details.
(2)
. Observe
”Pin Con-
62.
61
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