ATMEGA649P-AU Atmel, ATMEGA649P-AU Datasheet - Page 199
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA649P-AU
Manufacturer Part Number
ATMEGA649P-AU
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA649P-AU
Manufacturer:
AT
Quantity:
20 000
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19.11 Register Description
19.11.1
19.11.2
8284A–AVR–10/10
UDRn – USART I/O Data Register n
UCSRnA – USART Control and Status Register n A
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the UDRn Register location. Reading the
UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-
Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions
(SBIC and SBIS), since these also will change the state of the FIFO.
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
RXCn
R/W
R
7
0
7
0
TXCn
R/W
R/W
6
0
6
0
UDREn
R/W
5
0
R
5
1
R/W
FEn
4
0
R
RXBn[7:0]
4
0
TXBn[7:0]
R/W
DORn
3
0
R
3
0
R/W
2
0
UPEn
R
2
0
R/W
1
0
U2Xn
R/W
1
0
R/W
0
0
MPCMn
R/W
0
0
UDRn (Read)
UDRn (Write)
UCSRnA
199
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