ATMEGA649P-AU Atmel, ATMEGA649P-AU Datasheet - Page 250
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA649P-AU
Manufacturer Part Number
ATMEGA649P-AU
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA649P-AU
Manufacturer:
AT
Quantity:
20 000
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23.5.3
8284A–AVR–10/10
LCDFRR – LCD Frame Rate Register
Table 23-3.
Note:
• Bit 7 – Reserved Bit
This bit is reserved and will always read as zero.
• Bits 6:4 – LCDPS[2:0]: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD[2:0]). The different selections are shown in
23-4 on page
ing the LCD module.
Table 23-4.
Bit
(0xE6)
Read/Write
Initial Value
LCDPM3
LCDPS2
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1. LCDPM3 is reserved and will always read as zero in ATmega329A/329PA/649A/649P.
LCDPM2
250. Together they determine the prescaled LCD clock (clk
LCDPS1
LCD Port Mask (Values in bold are only available in
ATmega3290A/3290PA/6490A/6490P) (Continued)
LCD Prescaler Select
R
7
–
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
LCDPS2
R/W
LCDPM1
6
0
LCDPS0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
LCDPS1
R/W
5
0
LCDPM0
Output from
Prescaler
clk
clk
clk
clk
clk
clk
1
0
1
0
1
0
1
0
1
0
1
0
1
LCDPS0
LCD
LCD
LCD
R/W
LCD
LCD
LCD
4
0
/128
/256
/512
/16
/64
/N
I/O Port in Use as
R
Segment Driver
3
–
0
Applied Prescaled LCD Clock Frequency
SEG0:36
SEG0:38
SEG0:39
SEG0:18
SEG0:20
SEG0:22
SEG0:23
SEG0:24
SEG0:26
SEG0:28
SEG0:30
SEG0:32
SEG0:34
when LCDCD2:0 = 0, Duty = 1/4, and
LCDCD2
R/W
2
0
Frame Rate = 64 Hz
LCDCD1
R/W
130 kHz
260 kHz
8.1 kHz
1
0
33 kHz
66 kHz
LCD_PS
Maximum Number
LCDCD0
of Segments
), which is clock-
R/W
0
0
19
21
23
24
25
27
29
31
33
35
37
39
40
LCDFRR
Table
250
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