ATMEGA649P-AU Atmel, ATMEGA649P-AU Datasheet - Page 173
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA649P-AU
Manufacturer Part Number
ATMEGA649P-AU
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA649P-AU
Manufacturer:
AT
Quantity:
20 000
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18.5
18.5.1
8284A–AVR–10/10
Register Description
SPCR – SPI Control Register
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
tionality is summarized below:
Table 18-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
The CPOL functionality is summarized below:
Table 18-4.
Bit
0x2C (0x4C)
Read/Write
Initial Value
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
CPOL
CPHA
CPOL Functionality
CPHA Functionality
0
1
0
1
SPIE
R/W
7
0
Figure 18-3
SPE
R/W
6
0
and
DORD
R/W
5
0
Figure 18-3
Figure 18-4 on page 172
Leading Edge
Leading Edge
MSTR
Sample
Falling
Rising
R/W
Setup
4
0
and
CPOL
R/W
3
0
Figure 18-4 on page 172
CPHA
R/W
2
0
for an example. The CPOL func-
SPR1
R/W
1
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
SPR0
R/W
for an example.
0
0
SPCR
173
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