AT90USB646-AUR Atmel, AT90USB646-AUR Datasheet - Page 385

• Manufacturer Part Number: AT90USB646-AUR
• Description: MCU AVR 64K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB646-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 29-16. Serial Programming Instruction Set (Continued)
Note:
29.8.2
29.9
29.9.1
7593K–AVR–11/09
Instruction
Read Extended Fuse Bits
Read Calibration Byte
Poll RDY/BSY
a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in,
x = don’t care
Programming via the JTAG Interface
Serial Programming Characteristics
Programming Specific JTAG Instructions
For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page
403.
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared.
Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-
tem Programming via the JTAG interface. Note that this technique can not be used when using
the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-
icated for this purpose.
During programming the clock frequency of the TCK Input must be less than the maximum fre-
quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input
into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
0101 0000
0011 1000
1111 0000
Byte 1
0000 1000
000x xxxx
0000 0000
Byte 2
Instruction Format
Figure
xxxx xxxx
0000 0000
xxxx xxxx
Byte 3
29-12.
oooo oooo
oooo oooo
xxxx xxxo
Byte4
Operation
Read Extended Fuse bits. “0” = pro-
grammed, “1” = unprogrammed. See
Table 29-3 on page 367
Read Calibration Byte
If o = “1”, a programming operation is
still busy. Wait until this bit returns to
“0” before applying another command.
AT90USB64/128
for details.
385