AT90USB646-AUR Atmel, AT90USB646-AUR Datasheet - Page 147
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AT90USB646-AUR
Manufacturer Part Number
AT90USB646-AUR
Description
MCU AVR 64K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB646-MU.pdf
(461 pages)
Specifications of AT90USB646-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3
14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1
14.10.20 Timer/Counter3 Interrupt Flag Register – TIFR3
7593K–AVR–11/09
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
7
–
R
0
7
–
R
0
7
–
R
0
(See “Interrupts” on page
(See “Interrupts” on page
(See “Interrupts” on page
6
–
R
0
6
–
R
0
6
–
R
0
68.) is executed when the TOVn Flag, located in TIFRn, is set.
5
ICIE3
R/W
0
5
ICF1
R/W
0
5
ICF3
R/W
0
68.) is executed when the ICFn Flag, located in TIFRn, is set.
4
–
R
0
4
–
R
0
4
–
R
0
68.) is executed when the OCFnC Flag, located in
68.) is executed when the OCFnB Flag, located in
68.) is executed when the OCFnA Flag, located in
3
OCIE3
C
R/W
0
3
OCF1C
R/W
0
3
OCF3C
R/W
0
2
OCIE3B
R/W
0
2
OCF1B
R/W
0
2
OCF3B
R/W
0
1
OCF1A
R/W
0
1
OCF3A
R/W
0
1
OCIE3A
R/W
0
AT90USB64/128
0
TOV1
R/W
0
0
TOV3
R/W
0
0
TOIE3
R/W
0
TIFR1
TIFR3
TIMSK3
147
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