AT90USB646-AUR Atmel, AT90USB646-AUR Datasheet - Page 206

• Manufacturer Part Number: AT90USB646-AUR
• Description: MCU AVR 64K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB646-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
1.
19. USART in SPI Mode
19.1
206
Baud
Rate
(bps)
2400
4800
9600
14.4k
19.2k
28.8k
38.4k
57.6k
76.8k
115.2k
230.4k
250k
0.5M
1M
Max.
(1)
UBRR = 0, Error = 0.0%
Overview
AT90USB64/128
UBRR
416
207
103
68
51
34
25
16
12
8
3
3
1
0
U2Xn = 0
1 Mbps
f
osc
Error
-0.1%
-0.8%
-3.5%
0.6%
0.2%
0.2%
2.1%
0.2%
0.0%
0.2%
0.2%
8.5%
0.0%
0.0%
= 16.0000 MHz
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow-
ing features:
•
•
•
•
•
•
•
•
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
Full Duplex, Three-wire Synchronous Data Transfer
Master Operation
Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
LSB First or MSB First Data Transfer (Configurable Data Order)
Queued Operation (Double Buffered)
High Resolution Baud Rate Generator
High Speed Operation (fXCKmax = fCK/2)
Flexible Interrupt Generation
UBRR
832
416
207
138
103
68
51
34
25
16
8
7
3
1
U2Xn = 1
2 Mbps
Error
-0.1%
-0.1%
-0.8%
-3.5%
0.0%
0.2%
0.2%
0.6%
0.2%
0.2%
2.1%
0.0%
0.0%
0.0%
UBRR
479
239
119
79
59
39
29
19
14
9
4
4
–
–
1.152 Mbps
U2Xn = 0
f
osc
Error
-7.8%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
–
–
= 18.4320 MHz
UBRR
959
479
239
159
119
79
59
39
29
19
9
8
4
–
2.304 Mbps
U2Xn = 1
Error
-7.8%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
2.4%
–
UBRR
520
259
129
86
64
32
21
15
10
42
4
4
–
–
1.25 Mbps
U2Xn = 0
f
osc
Error
-0.2%
-1.4%
-1.4%
-1.4%
0.0%
0.2%
0.2%
0.2%
0.9%
1.7%
8.5%
0.0%
–
–
= 20.0000 MHz
UBRR
1041
520
259
173
129
64
42
32
10
86
21
9
4
–
7593K–AVR–11/09
U2Xn = 1
2.5 Mbps
Error
-0.2%
-0.2%
-1.4%
-1.4%
-1.4%
0.0%
0.2%
0.2%
0.2%
0.9%
0.0%
0.0%
0.0%
–