AT32UC3B164-AUT Atmel, AT32UC3B164-AUT Datasheet - Page 665
![IC MCU AVR32 64KB FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B164-AUT
Manufacturer Part Number
AT32UC3B164-AUT
Description
IC MCU AVR32 64KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
28
Ram Memory Size
16KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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32059I–06/2010
4. Read Modify Write (RMW) instructions on data outside the internal RAM does not
5. Need two NOPs instruction after instructions masking interrupts
6. Clock connection table on Rev B
Figure 31-1. Timer/Counter clock connections on RevB
7. Spurious interrupt may corrupt core SR mode to exception
8. CPU cannot operate on a divided slow clock (internal RC oscillator)
9. LDM instruction with PC in the register list and without ++ increments Rp
Source
Internal
External
work
Read Modify Write (RMW) instructions on data outside the internal RAM does not work.
Fix/Workaround
Do not perform RMW instructions on data outside the internal RAM.
The instructions following in the pipeline the instruction masking the interrupt through SR
may behave abnormally.
Fix/Workaround
Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR
Here is the table of Rev B
If the rules listed in the chapter `Masking interrupt requests in peripheral modules' of the
AVR32UC Technical Reference Manual are not followed, a spurious interrupt may occur. An
interrupt context will be pushed onto the stack while the core SR mode will indicate an
exception. A RETE instruction would then corrupt the stack.
Fix/Workaround
Follow the rules of the AVR32UC Technical Reference Manual. To increase software
robustness, if an exception mode is detected at the beginning of an interrupt handler,
change the stack interrupt context to an exception context and issue a RETE instruction.
CPU cannot operate on a divided slow clock (internal RC oscillator).
Fix/Workaround
Do not run the CPU on a divided slow clock.
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Connection
32KHz Oscillator
PBA Clock / 4
PBA Clock / 8
PBA Clock / 16
PBA Clock / 32
AT32UC3B
665
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