AT32UC3B164-AUT Atmel, AT32UC3B164-AUT Datasheet - Page 440

• Manufacturer Part Number: AT32UC3B164-AUT
• Description: IC MCU AVR32 64KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B164-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 28
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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32059I–06/2010
CRCERRI: CRC Error Interrupt
OVERFI: Overflow Interrupt
NAKINI: NAKed IN Interrupt
NAKOUTI: NAKed OUT Interrupt
UNDERFI: Underflow Interrupt
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT
This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not
Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one.
bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.
packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the
first bytes of the packet that fit in.
interrupt if NAKINE is one.
interrupt if NAKOUTE is one.
UNDERFE is one.
automatically sent by the USBB.
fast enough. The packet is lost.
AT32UC3B
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