PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 77
![IC PIC MCU FLASH 4KX16 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC18LF1330-I/SO
Manufacturer Part Number
PIC18LF1330-I/SO
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18LF1330-I/SO
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1330-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- PIC18F1230-IP PDF datasheet #6
- Current page: 77 of 312
- Download datasheet (6Mb)
7.0
The data EEPROM is readable and writable during
normal operation over the entire V
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
• EECON1
• EECON2
• EEDATA
• EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 128 bytes of data EEPROM with
an address range from 00h to FFh.
The EEPROM data memory is rated for high erase/
write cycle endurance. A byte write automatically
erases the location and writes the new data (erase-
before-write). The write time is controlled by an on-chip
timer. The write time will vary with voltage and
temperature, as well as from chip-to-chip. Please
refer to parameter D122 (Table 22-1 in Section 22.0
“Electrical Characteristics”) for exact limits.
7.1
The EEPROM Address register can address 256 bytes
of data EEPROM.
7.2
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
© 2007 Microchip Technology Inc.
DATA EEPROM MEMORY
EECON1 and EECON2 Registers
EEADR Register
DD
range. The data
Advance Information
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled; the WR bit cannot be set while the WREN bit
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.
Firmware should keep the WREN bit clear at all times,
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is
interrupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It is
necessary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
Note:
PIC18F1230/1330
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
DS39758C-page 75
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