PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 128
![IC PIC MCU FLASH 4KX16 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC18LF1330-I/SO
Manufacturer Part Number
PIC18LF1330-I/SO
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18LF1330-I/SO
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1330-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- PIC18F1230-IP PDF datasheet #6
- Current page: 128 of 312
- Download datasheet (6Mb)
PIC18F1230/1330
13.6.2
The three PWM Duty Cycle registers are double-
buffered to allow glitchless updates of the PWM
outputs. For each duty cycle block, there is a Duty
Cycle Buffer register that is accessible by the user and
a second Duty Cycle register that holds the actual
compare value used in the present PWM period.
In Edge-Aligned PWM Output mode, a new duty cycle
value will be updated whenever a PTMR match with the
PTPER register occurs and PTMR is reset, as shown in
Figure 13-12. Also, the contents of the duty cycle buffers
are automatically loaded into the Duty Cycle registers
when the PWM time base is disabled (PTEN = 0).
When the PWM time base is in the Continuous Up/
Down Count mode, new duty cycle values will be
updated when the value of the PTMR register is zero
and the PWM time base begins to count upwards. The
contents of the duty cycle buffers are automatically
loaded into the Duty Cycle registers when the PWM
time base is disabled (PTEN = 0). Figure 13-13 shows
the timings when the duty cycle update occurs for the
Continuous Up/Down Count mode. In this mode, up to
one entire PWM period is available for calculating and
loading the new PWM duty cycle before changes take
effect.
When the PWM time base is in the Continuous Up/
Down Count mode with double updates, new duty cycle
values will be updated when the value of the PTMR
register is zero and when the value of the PTMR
register matches the value in the PTPER register. The
contents of the duty cycle buffers are automatically
loaded into the Duty Cycle registers during both of the
previously described conditions. Figure 13-14 shows
the duty cycle updates for Continuous Up/Down Count
mode with double updates. In this mode, up to half of a
PWM period is available for calculating and loading the
new PWM duty cycle before changes take effect.
FIGURE 13-13:
DS39758C-page 126
DUTY CYCLE REGISTER BUFFERS
PWM Output
PTMR Value
DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE
Advance Information
Duty Cycle Value Loaded from Buffer Register
13.6.3
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running mode
or the Single-Shot mode. For edge-aligned PWM
outputs, the output for a given PWM channel has a
period specified by the value loaded in PTPER and a
duty cycle specified by the appropriate Duty Cycle
register (see Figure 13-12). The PWM output is driven
active at the beginning of the period (PTMR = 0) and is
driven inactive when the value in the Duty Cycle register
matches PTMR. A new cycle is started when PTMR
matches the PTPER, as explained in the PWM period
section.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 13-12:
Active at
Beginning
of Period
PTPER
New Value Written to Duty Cycle Buffer
PDCx
PDCx
(new)
(old)
0
EDGE-ALIGNED PWM
PTMR
Value
Duty Cycle
Period
EDGE-ALIGNED PWM
© 2007 Microchip Technology Inc.
New Duty Cycle Latched
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