PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 68
![IC PIC MCU FLASH 4KX16 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC18LF1330-I/SO
Manufacturer Part Number
PIC18LF1330-I/SO
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18LF1330-I/SO
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1330-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- PIC18F1230-IP PDF datasheet #6
- Current page: 68 of 312
- Download datasheet (6Mb)
PIC18F1230/1330
FIGURE 6-2:
6.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 19.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
DS39758C-page 66
Control Registers
Note 1: Table Pointer actually points to one of 8 holding registers, the address of which is determined by
write
TBLPTRU
EECON1 AND EECON2 REGISTERS
EEPROM
and
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
Table Pointer
TABLE WRITE OPERATION
TBLPTRH
erase
memory.
sequences.
(1)
TBLPTRL
Program Memory
(TBLPTR)
When
Advance Information
Reading
set,
Instruction: TBLWT*
Holding Registers
Program Memory
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Note:
Note:
During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset, or a write operation was
attempted improperly.
The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
© 2007 Microchip Technology Inc.
Table Latch (8-bit)
TABLAT
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