PIC18F2331-E/SP Microchip Technology, PIC18F2331-E/SP Datasheet - Page 287

• Manufacturer Part Number: PIC18F2331-E/SP
• Description: IC MCU FLASH 4KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2331-E/SP

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

22.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a Boot Block of 512 bytes. The
remainder of the memory is divided into four blocks on
binary boundaries.
FIGURE 22-5:
TABLE 22-3:
© 2007 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend:
Note 1:
®
devices.
File Name
Program Verification and
Code Protection
(PIC18F2331/4331)
Unimplemented
Unimplemented in PIC18F2331/2431 devices; maintain this bit set.
Shaded cells are unimplemented.
Boot Block
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
8 Kbytes
Read ‘0’s
Block 0
Block 1
SUMMARY OF CODE PROTECTION REGISTERS
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431
WRTD
Bit 7
CPD
—
—
—
—
0000h
0FFFh
0200h
0FFFh
1000h
1FFFh
3FFFh
Address
Range
EBTRB
WRTB
Bit 6
CPB
—
—
—
PIC18F2331/2431/4331/4431
MEMORY SIZE/DEVICE
(PIC18F2431/4431)
Preliminary
WRTC
16 Kbytes
Boot Block
Bit 5
Block 0
Block 1
Block 2
Block 3
—
—
—
—
—
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 22-5 shows the program memory organization
for 8 and 16-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
Bit 4
—
—
—
—
—
—
0000h
01FFh
0200h
0FFFh
1000h
1FFFh
2000h
2FFFh
3000h
3FFFh
Address
Range
EBTR3
WRT3
CP3
Bit 3
—
—
—
(1)
(1)
(1)
EBTR2
Block Code Protection
WRT2
CP2
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Bit 2
—
—
—
Controlled By:
(1)
(1)
(1)
EBTR1
WRT1
Bit 1
CP1
DS39616C-page 285
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—