ATMEGA325PV-10MU Atmel, ATMEGA325PV-10MU Datasheet - Page 21

• Manufacturer Part Number: ATMEGA325PV-10MU
• Description: IC MCU AVR 32K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325PV-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA325PV-8MU; ATMEGA325PV-8MU

7.3.1
7.4
7.4.1
8023F–AVR–07/09
EEPROM Data Memory
Data Memory Access Times
EEPROM Read/Write Access
these addressing modes. The Register File is described in
page
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 7-3.
The ATmega325P/3250P contains 1K bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page
The EEPROM Access Registers are accessible in the I/O space.
14.
285,
page
Address
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
291, and
WR
CPU
RD
page 274
Compute Address
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
(2048 x 8)
T1
Memory Access Instruction
respectively.
Address valid
0x08FF
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
CPU
T2
cycles as described in
ATmega325P/3250P
”General Purpose Register File” on
Next Instruction
T3
Figure
7-3.
21