ATMEGA325PV-10MU Atmel, ATMEGA325PV-10MU Datasheet - Page 202

• Manufacturer Part Number: ATMEGA325PV-10MU
• Description: IC MCU AVR 32K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325PV-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA325PV-8MU; ATMEGA325PV-8MU

202
ATmega325P/3250P
Table 19-2
used for the Shift Register and the 4-bit counter.
Table 19-2.
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to
increment by one, provided that the USICS1:0 bits are set to zero and by doing so the software
clock strobe option is selected. The output will change immediately when the clock strobe is exe-
cuted, i.e., in the same instruction cycle. The value shifted into the Shift Register is sampled the
previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independent of the setting in the Data Direction Register, but if the PORT value is
to be shown on the pin the DDRE4 must be set as output (to one). This feature allows easy clock
generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
USICS1
0
0
0
1
1
1
1
shows the relationship between the USICS1:0 and USICLK setting and clock source
USICS0
Relations between the USICS1:0 and USICLK Setting
0
0
1
0
1
0
1
USICLK
0
1
X
0
0
1
1
Shift Register Clock Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, positive edge
External, negative edge
External, positive edge
External, negative edge
Table
19-2).
4-bit Counter Clock Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, both edges
External, both edges
Software clock strobe (USITC)
Software clock strobe (USITC)
8023F–AVR–07/09