ATMEGA325PV-10MU Atmel, ATMEGA325PV-10MU Datasheet - Page 16

• Manufacturer Part Number: ATMEGA325PV-10MU
• Description: IC MCU AVR 32K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325PV-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA325PV-8MU; ATMEGA325PV-8MU

6.6.1
6.7
16
Instruction Execution Timing
ATmega325P/3250P
SPH and SPL – Stack Pointer High and Stack Pointer Low
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 1
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 1. The Parallel Instruction Fetches and Instruction Executions
Figure 2
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 2. Single Cycle ALU Operation
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the parallel instruction fetches and instruction executions enabled by the Har-
shows the internal timing concept for the Register File. In a single clock cycle an ALU
Result Write Back
SP15
SP7
R/W
R/W
15
7
0
0
clk
clk
CPU
CPU
SP14
SP6
R/W
R/W
14
6
0
0
SP13
R/W
R/W
SP5
CPU
13
5
0
0
T1
T1
, directly generated from the selected clock source for the
SP12
SP4
R/W
R/W
12
4
0
0
SP11
T2
R/W
R/W
SP3
T2
11
3
0
0
SP10
SP2
R/W
R/W
10
2
0
0
T3
T3
R/W
SP9
SP1
R/W
9
1
0
0
SP8
SP0
R/W
R/W
8
0
0
0
8023F–AVR–07/09
T4
T4
SPH
SPL