ATMEGA325PV-10MU Atmel, ATMEGA325PV-10MU Datasheet - Page 105
ATMEGA325PV-10MU
Manufacturer Part Number
ATMEGA325PV-10MU
Description
IC MCU AVR 32K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA3250P-20AU.pdf
(364 pages)
Specifications of ATMEGA325PV-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA325PV-8MU
ATMEGA325PV-8MU
ATMEGA325PV-8MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA325PV-10MU
Manufacturer:
ATMEL
Quantity:
3 500
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14.10.5
14.10.6
8023F–AVR–07/09
TIFR0 – Timer/Counter 0 Interrupt Flag Register
GTCCR – General Timer/Counter Control Register
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register” on page
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the
0 Interrupt Flag Register” on page
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the
data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare match Interrupt
Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In
phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at
0x00.
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,
and the Timer/Counters start counting simultaneously.
Bit
0x15 (0x35)
Read/Write
Initial Value
Bit
0x23 (0x43)
Read/Write
Initial Value
TSM
R/W
7
0
R
7
–
0
R
6
–
0
R
6
–
0
105.
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
105.
R
3
–
0
R
3
–
0
ATmega325P/3250P
R
2
–
0
R
2
–
0
OCF0A
R/W
PSR2
”TIFR0 – Timer/Counter
1
0
R/W
1
0
TOV0
PSR10
R/W
R/W
0
0
0
0
”TIFR0 –
GTCCR
TIFR0
105
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