AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 246

• Manufacturer Part Number: AT90USB162-16MU
• Description: MCU AVR USB 16K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Reading the
Calibration Byte
Parallel Programming
Characteristics
246
The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on
page 240 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
Figure 101. Parallel Programming Timing, Including some General Timing Requirements
Figure 102. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
PAGEL
(DATA, XA0/1, BS1, BS2)
XTAL1
DATA
BS1
XA0
XA1
1. The timing requirements shown in Figure 101 (i.e., t
ing operation.
Data & Contol
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
XTAL1
(LOW BYTE)
WR
t
t
BVPH
DVXH
LOAD DATA
(LOW BYTE)
DATA (Low Byte)
t
t
XHXL
PHPL
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
t
BVWL
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
DVXH
t
WLWH
t
XLPH
WLRL
, t
LOAD DATA
XHXL
, and t
t
PLXH
t
WLBX
XLDX
LOAD ADDRESS
(LOW BYTE)
) also apply to load-
ADDR1 (Low Byte)
7707A–AVR–01/07
t
WLRH
(1)