AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 229

• Manufacturer Part Number: AT90USB162-16MU
• Description: MCU AVR USB 16K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

AT90USB82/162 Boot
Loader Parameters
Table 29. Boot Size Configuration
7707A–AVR–01/07
16Kb
8Kb
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1024 bytes
2048 bytes
4096 bytes
1024 bytes
2048 bytes
4096 bytes
512 bytes
512 bytes
In Table 29 through Table 31, the parameters used in the description of the Self-Programming
are given.
Return:
Do_spm:
Wait_spm:
Wait_ee:
; return to RWW section
; verify that RWW section is safe to read
in
sbrs temp1, RWWSB
ret
; re-enable the RWW section
ldi
call Do_spm
rjmp Return
; check for previous SPM complete
in
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
cli
; check that no EEPROM write access is present
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
()
(16k)
16
32
16
32
4
8
4
8
temp1, SPMCSR
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
temp1, SPMCSR
temp2, SREG
SPMCSR, spmcrval
SREG, temp2
0x0000 - 0x3DFF
0x0000 - 0x3BFF
0x0000 - 0x37FF
0x0000 - 0x2FFF
0x0000 - 0x1DFF
0x0000 - 0x1BFF
0x0000 - 0x17FF
0x0000 - 0x0FFF
; If RWWSB is set, the RWW section is not ready yet
0x3E00 - 0x3FFF
0x3C00 - 0x3FFF
0x3800 - 0x3FFF
0x3000 - 0x3FFF
0x1E00 - 0x1FFF
0x1C00 - 0x1FFF
0x1800 - 0x1FFF
0x1000 - 0x1FFF
0x3DFF
0x1DFF
0x3BFF
0x2FFF
0x1BFF
0x0FFF
0x37FF
0x17FF
0x3C00
0x1C00
0x3E00
0x1E00
0x3800
0x3000
0x1800
0x1000
229