AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 166

• Manufacturer Part Number: AT90USB162-16MU
• Description: MCU AVR USB 16K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

USART Control and
Status Register n D –
UCSRnD
USART Baud Rate
Registers – UBRRLn
and UBRRHn
166
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 7. UCSZn Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 8. UCPOLn Bit Settings
• Bits 1 – CTSEN : USART CTS Enable
Set this bit to one by firmware to enable the transmission flow control (CTS). Transmission is
allowed if CTS = 0.
Set this bit to zero by firmware to disable the transmission flow control (CTS). Transmission is
always allowed.
• Bits 0 – RTSEN : USART RTS Enable
Set this bit to one by firmware to enable the receive flow control (RTS).
Set this bit to zero by firmware to disable the receive flow control (RTS).
Bit
Read/Write
Initial Value
Bit
UCPOLn
UCSZn2
0
1
0
0
0
0
1
1
1
1
7
-
R/W
0
15
–
UBRR[7:0]
7
Transmitted Data Changed (Output
of TxDn Pin)
Rising XCKn Edge
Falling XCKn Edge
6
-
R/W
0
14
–
6
UCSZn1
0
0
1
1
0
0
1
1
13
–
5
5
-
R/W
0
12
–
4
4
-
R/W
0
UCSZn0
0
1
0
1
0
1
0
1
11
UBRR[11:8]
3
3
-
R/W
0
Received Data Sampled (Input on
RxDn Pin)
Rising XCKn Edge
Falling XCKn Edge
10
2
2
-
R/W
0
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
9
1
1
CTSEN
R/W
0
8
0
0
RTSEN
R/W
0
UBRRHn
UBRRLn
UCSRnD
7707A–AVR–01/07