ATMEGA32U4-AUR Atmel, ATMEGA32U4-AUR Datasheet - Page 412
![MCU AVR 16K FLASH 16MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32U4-AUR
Manufacturer Part Number
ATMEGA32U4-AUR
Description
MCU AVR 16K FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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32. Instruction Set Summary
7766F–AVR–11/10
Mnemonics
FMULSU
MULSU
FMULS
EICALL
RCALL
EIJMP
BREQ
BRCC
BRGE
BRHC
ADIW
MULS
FMUL
RJMP
ICALL
CPSE
SBRC
SBRS
BRBS
BRBC
BRNE
BRCS
BRSH
BRLO
BRPL
BRHS
BRTS
BRTC
BRVS
SBIW
CALL
BRMI
BRLT
SUBI
SBCI
ANDI
COM
IJMP
RETI
SBIC
SBIS
ADD
ADC
SUB
SBC
AND
EOR
NEG
SBR
CBR
DEC
CLR
SER
MUL
JMP
RET
CPC
TST
ORI
INC
CPI
OR
CP
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rdl,K
Rd, K
Rd, K
Rdl,K
Rd, K
Rd, K
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
Rd
Rd
Rd
Rd
Rd
Rd
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
Fractional Multiply Signed with Unsigned
Subtract with Carry Constant from Reg.
Logical AND Register and Constant
Branch if Greater or Equal, Signed
Logical OR Register and Constant
Compare Register with Immediate
Branch if Less Than Zero, Signed
Subtract with Carry two Registers
Branch if Half Carry Flag Cleared
Skip if Bit in I/O Register Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Multiply Signed with Unsigned
Extended Indirect Jump to (Z)
Branch if Overflow Flag is Set
Add with Carry two Registers
Skip if Bit in Register Cleared
Branch if Status Flag Cleared
Branch if Half Carry Flag Set
Fractional Multiply Unsigned
Extended Indirect Call to (Z)
Skip if Bit in Register is Set
Fractional Multiply Signed
Branch if Same or Higher
Branch if Status Flag Set
Relative Subroutine Call
Branch if T Flag Cleared
Add Immediate to Word
Exclusive OR Registers
Branch if Carry Cleared
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Test for Zero or Minus
Direct Subroutine Call
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
One’s Complement
Two’s Complement
Indirect Jump to (Z)
Branch if Not Equal
Branch if Carry Set
Add two Registers
Indirect Call to (Z)
Subroutine Return
Multiply Unsigned
Interrupt Return
Branch if Lower
Multiply Signed
Branch if Equal
Branch if Minus
Description
Clear Register
Relative Jump
Branch if Plus
Set Register
Direct Jump
Decrement
Increment
Compare
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (Rd = Rr) PC ← PC + 2 or 3
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
R1:R0 ← (Rd x Rr)
R1:R0 ← (Rd x Rr)
R1:R0 ← (Rd x Rr)
Rdh:Rdl ← Rdh:Rdl + K
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • (0xFF - K)
Rd ← Rd + Rr + C
PC ← PC + k + 1
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
Rd ← Rd - Rr - C
Rd ← 0xFF − Rd
PC ← PC + k + 1
Rd ← 0x00 − Rd
Rd ← Rd - K - C
Rd ← Rd ⊕ Rd
PC ←(EIND:Z)
PC ←(EIND:Z)
Rd ← Rd ⊕ Rr
Rd ← Rd • Rd
Rd ← Rd + Rr
Rd ← Rd • Rr
Rd ← Rd v Rr
PC ← STACK
PC ← STACK
Rd ← Rd - Rr
Rd ← Rd • K
Rd ← Rd v K
Rd ← Rd v K
Rd ← Rd + 1
Rd ← Rd − 1
Operation
Rd ← Rd - K
Rd − Rr − C
Rd ← 0xFF
PC ← Z
PC ← Z
PC ← k
PC ← k
Rd − Rr
Rd − K
<< 1
<< 1
<< 1
ATmega16/32U4
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V
Flags
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
I
#Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
4
4
4
5
5
5
1
1
1
412
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