ATMEGA32U4-AUR Atmel, ATMEGA32U4-AUR Datasheet - Page 26
![MCU AVR 16K FLASH 16MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32U4-AUR
Manufacturer Part Number
ATMEGA32U4-AUR
Description
MCU AVR 16K FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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5.4
5.4.1
5.4.2
5.4.3
5.4.4
7766F–AVR–11/10
I/O Memory
General Purpose I/O Registers
General Purpose I/O Register 2 – GPIOR2
General Purpose I/O Register 1 – GPIOR1
General Purpose I/O Register 0 – GPIOR0
The I/O space definition of the ATmega16U4/ATmega32U4 is shown in
page
All ATmega16U4/ATmega32U4 I/Os and peripherals are placed in the I/O space. All I/O loca-
tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data
space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16U4/ATmega32U4 is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-
tions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega16U4/ATmega32U4 contains three General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global vari-
ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
408.
7
MSB
R/W
0
7
MSB
R/W
0
7
MSB
R/W
0
6
R/W
0
6
R/W
0
6
R/W
0
5
R/W
0
5
R/W
0
5
R/W
0
4
R/W
0
4
R/W
0
4
R/W
0
3
0
3
0
3
0
R/W
R/W
R/W
2
R/W
0
2
R/W
0
2
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
ATmega16/32U4
0
LSB
R/W
0
0
LSB
R/W
0
0
LSB
R/W
0
“Register Summary” on
GPIOR2
GPIOR1
GPIOR0
26
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