PIC16F1947-I/PT Microchip Technology, PIC16F1947-I/PT Datasheet - Page 324

• Manufacturer Part Number: PIC16F1947-I/PT
• Description: IC MCU 8BIT FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1947-I/PT

• Core Size: 8-Bit
• Program Memory Size: 28KB (16K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F/LF1946/47
25.4.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RCxIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 25-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS41414B-page 324
BAUD1CON
BAUD2CON
INTCON
PIE1
PIE4
PIR1
PIR4
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
TX2STA
Legend:
never Idle
Name
Reception”), with the following exceptions:
*
Page provides register information.
— = unimplemented locations, read as ‘ 0 ’. Shaded bits are not used for synchronous slave reception.
EUSART Synchronous Slave
Reception
TMR1GIE
TMR1GIF
ABDOVF
ABDOVF
SPEN
SPEN
CSRC
CSRC
Bit 7
GIE
—
—
(Section 25.4.1.6 “Synchronous
RCIDL
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
RX9
TX9
TX9
—
—
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
TMR0IE
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
RC2IE
RC2IF
SREN
SREN
TXEN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART1 Receive Register
EUSART2 Receive Register
Preliminary
TX2IE
CREN
CREN
SYNC
SYNC
SCKP
SCKP
TX2IF
INTE
TXIE
Bit 4
TXIF
ADDEN
ADDEN
SENDB
SENDB
BRG16
BRG16
25.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
SSPIE
SSPIF
IOCIE
Bit 3
—
—
Set the SYNC and SPEN bits and clear the
CSRC bit.
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCxIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCxIF bit will be set when reception is
complete. An interrupt will be generated if the
RCxIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCxREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IE
CCP1IF
BRGH
BRGH
FERR
FERR
Bit 2
Synchronous Slave Reception
Set-up:
—
—
—
—
TMR2IE
TMR2IF
BCL2IE
BCL2IF
OERR
OERR
TRMT
TRMT
 2010 Microchip Technology Inc.
WUE
WUE
Bit 1
INTF
TMR1IE
TMR1IF
ABDEN
ABDEN
SSP2IE
SSP2IF
IOCIF
RX9D
RX9D
TX9D
TX9D
Bit 0
Register
on Page
302*
302*
309*
309*
309*
309*
308
308
307
307
306
306
93
94
97
98
97