PIC16F1947-I/PT Microchip Technology, PIC16F1947-I/PT Datasheet - Page 300
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PIC16F1947-I/PT
Manufacturer Part Number
PIC16F1947-I/PT
Description
IC MCU 8BIT FLASH 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(46 pages)
3.PIC16LF1946-IPT.pdf
(448 pages)
4.PIC16LF1946-IPT.pdf
(6 pages)
5.PIC16F1946-IPT.pdf
(8 pages)
6.PIC16F1946-EPT.pdf
(440 pages)
Specifications of PIC16F1947-I/PT
Core Size
8-Bit
Program Memory Size
28KB (16K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
1024Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1946-IPT PDF datasheet #3
- PIC16LF1946-IPT PDF datasheet #4
- PIC16F1946-IPT PDF datasheet #5
- PIC16F1946-EPT PDF datasheet #6
- Current page: 300 of 448
- Download datasheet (4Mb)
PIC16F/LF1946/47
25.1.1.5
The TRMT bit of the TXxSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXxREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
25.1.1.6
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXxSTA register is set the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXxSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXxREG. All nine
bits of data will be transferred to the TSR shift register
immediately after the TXxREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See
Detection”
FIGURE 25-3:
DS41414B-page 300
Note:
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXxREG
(Transmit Buffer
(Transmit Shift
TXx/CKx
BRG Output
(Shift Clock)
TRMT bit
TXxIF bit
The TSR register is not mapped in data
memory, so it is not available to the user.
for more information on the Address mode.
TSR Status
Transmitting 9-Bit Characters
pin
ASYNCHRONOUS TRANSMISSION
Word 1
Transmit Shift Reg
Word 1
Section 25.1.2.8 “Address
1 T
CY
Start bit
bit 0
Preliminary
bit 1
Word 1
25.1.1.7
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
Baud Rate Generator
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the 8 Least Significant data bits are an address
when the receiver is set for address detection.
Set the CKTXP control bit if inverted transmit
data polarity is desired.
Enable the transmission by setting the TXEN
control bit. This will cause the TXxIF interrupt bit
to be set.
If interrupts are desired, set the TXxIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXxREG register. This
will start the transmission.
Asynchronous Transmission Set-up:
bit 7/8
2010 Microchip Technology Inc.
(BRG)”).
Stop bit
Section 25.3 “EUSART
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