DSPIC30F2011-20E/ML Microchip Technology, DSPIC30F2011-20E/ML Datasheet - Page 99
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DSPIC30F2011-20E/ML
Manufacturer Part Number
DSPIC30F2011-20E/ML
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011-20E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
DAF30-4 - DEVICE ATP FOR ICE4000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
14.2
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is ‘0’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 LSb of the
I2CADD register.
If the A10M bit is ‘1’, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value ‘11110 A9 A8’ (where
A9 and A8 are two Most Significant bits of I2CADD). If
that value matches, the next address will be compared
with the Least Significant 8 bits of I2CADD, as specified
in the 10-bit addressing protocol.
The 7-bit I
dsPIC30F are shown in
TABLE 14-1:
14.3
Once enabled (I2CEN = 1), the slave module will wait
for a Start bit to occur (i.e., the I
Following the detection of a Start bit, 8 bits are shifted
into I2CRSR and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the ris-
ing edge of SCL.
If an address match occurs, an acknowledgement will
be sent, and the slave event interrupt flag (SI2CIF) is
set on the falling edge of the ninth (ACK) bit. The
address match does not affect the contents of the
I2CRCV buffer or the RBF bit.
14.3.1
If the R_W bit received is a ‘1’, then the serial port will
go into Transmit mode. It will send ACK on the ninth bit
and then hold SCL to ‘0’ until the CPU responds by
writing to I2CTRN. SCL is released by setting the
SCLREL bit, and 8 bits of data are shifted out. Data bits
are shifted out on the falling edge of SCL, such that
SDA is valid during SCL high. The interrupt pulse is
sent on the falling edge of the ninth clock pulse,
regardless of the status of the ACK received from the
master.
© 2010 Microchip Technology Inc.
0x00
0x01-0x03
0x04-0x07
0x04-0x77
0x78-0x7b
0x7c-0x7f
I
I
2
2
C Module Addresses
C 7-bit Slave Mode Operation
SLAVE TRANSMISSION
2
C Slave Addresses supported by the
7-BIT I
ADDRESSES
General call address or start byte
Reserved
Hs-mode Master codes
Valid 7-bit addresses
Valid 10-bit addresses (lower 7
bits)
Reserved
Table
2
C™ SLAVE
14-1.
2
C module is ‘Idle’).
dsPIC30F2011/2012/3012/3013
14.3.2
If the R_W bit received is a ‘0’ during an address
match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF = 1), then
ACK is not sent; however, the interrupt pulse is
generated. In the case of an overflow, the contents of
the I2CRSR are not loaded into the I2CRCV.
14.4
In 10-bit mode, the basic receive and transmit
operations are the same as in the 7-bit mode. However,
the criteria for address match is more complex.
The I
addressed for a write operation with two address bytes
following a Start bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a 7-bit
address. The address detection protocol for the first byte
of a message address is identical for 7-bit and 10-bit
messages, but the bits being compared are different.
I2CADD holds the entire 10-bit address. Upon
receiving an address following a Start bit, I2CRSR
<7:3> is compared against a literal ‘11110’ (the default
10-bit address) and I2CRSR<2:1> are compared
against I2CADD<9:8>. If a match occurs and if
R_W = 0, the interrupt pulse is sent. The ADD10 bit will
be cleared to indicate a partial address match. If a
match fails or R_W = 1, the ADD10 bit is cleared and
the module returns to the Idle state.
The low byte of the address is then received and
compared with I2CADD<7:0>. If an address match
occurs, the interrupt pulse is generated and the ADD10
bit is set, indicating a complete 10-bit address match. If
an address match did not occur, the ADD10 bit is
cleared and the module returns to the Idle state.
Note:
2
C specification dictates that a slave must be
I
2
C 10-bit Slave Mode Operation
SLAVE RECEPTION
The I2CRCV will be loaded if the I2COV
bit = 1 and the RBF flag = 0. In this case,
a read of the I2CRCV was performed but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The acknowledgement is not
sent (ACK = 1) and the I2CRCV is
updated.
DS70139G-page 99