PIC16CE625-04/SS Microchip Technology, PIC16CE625-04/SS Datasheet - Page 60

• Manufacturer Part Number: PIC16CE625-04/SS
• Description: IC MCU OTP 2KX14 EE COMP 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE625-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• For Use With: 309-1016 - ADAPTER 20-SSOP TO 18-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

PIC16CE62X
10.5.1
External interrupt on RB0/INT pin is edge triggered;
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 10.8 for
details on SLEEP and Figure 10-19 for timing of
wake-up from SLEEP through RB0/INT interrupt.
10.5.2
An overflow (FFh
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 7.0.
FIGURE 10-16: INT PIN INTERRUPT TIMING
DS40182C-page 60
INSTRUCTION FLOW
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
enabled/disabled
2: Interrupt latency = 3-4 Tcy where T
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
RB0/INT INTERRUPT
TMR0 INTERRUPT
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3
Q1
Inst (PC-1)
Inst (PC)
00h) in the TMR0 register will
1
Q2
PC
by
Q3
4
setting/clearing
Q4
5
Q1
Inst (PC+1)
Inst (PC)
CY
Q2
1
= instruction cycle time.
PC+1
Q3
T0IE
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
10.5.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
10.5.4
See Section 8.6 for complete description of comparator
interrupts.
PC+1
—
Note:
Q3
PORTB INTERRUPT
COMPARATOR INTERRUPT
Q4
2
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
Q3
1999 Microchip Technology Inc.
Q4
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4