PIC16CE625-04/SS Microchip Technology, PIC16CE625-04/SS Datasheet - Page 33

• Manufacturer Part Number: PIC16CE625-04/SS
• Description: IC MCU OTP 2KX14 EE COMP 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE625-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• For Use With: 309-1016 - ADAPTER 20-SSOP TO 18-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

FIGURE 6-6:
6.5
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations: current address read, random
read, and sequential read.
6.6
The EEPROM contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the EEPROM
address with R/W bit set to one, the EEPROM issues
an acknowledge and transmits the eight bit data word.
The processor will not acknowledge the transfer, but
does generate a stop condition and the EEPROM dis-
continues transmission (Figure 6-7).
6.7
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
EEPROM as part of a write operation. After the word
address is sent, the processor generates a start condi-
tion following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again, but with the R/W bit set to a one. The
EEPROM will then issue an acknowledge and trans-
mits the eight bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-8).
1999 Microchip Technology Inc.
BUS ACTIVITY
PROCESSOR
SDA LINE
BUS ACTIVITY
Read Operation
Current Address Read
Random Read
PAGE WRITE
S
T
A
R
T
S
CONTROL
BYTE
A
C
K
ADDRESS (n)
WORD
A
C
K
6.8
Sequential reads are initiated in the same way as a ran-
dom read except that after the EEPROM transmits the
first data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-9).
To provide sequential reads, the EEPROM contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
6.9
The EEPROM employs a V
cuit, which disables the internal erase/write logic if the
V
The SCL and SDA inputs have Schmitt trigger and filter
circuits, which suppress noise spikes to assure proper
device operation even on a noisy bus.
DATAn
CC
is below 1.5 volts at nominal conditions.
Sequential Read
Noise Protection
A
C
K
DATAn + 1
PIC16CE62X
A
C
K
CC
threshold detector cir-
DATAn + 7
DS40182C-page 33
A
C
K
S
T
O
P
P