PIC18F65J15T-I/PT Microchip Technology, PIC18F65J15T-I/PT Datasheet - Page 227

• Manufacturer Part Number: PIC18F65J15T-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J15T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18F65J15T-I/PT; PIC18F65J15T-I/PTTR

19.4.7
In I
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 19-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
FIGURE 19-19:
TABLE 19-3:
© 2009 Microchip Technology Inc.
CY
2
C Master mode, the Baud Rate Generator (BRG)
) on the Q2 and Q4 clocks. In I
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
F
OSC
BAUD RATE
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
10 MHz
10 MHz
10 MHz
SCLx
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
2
CY
C Master mode, the
SSPM<3:0>
Reload
Control
CLKO
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
Reload
PIC18F87J10 FAMILY
19.4.7.1
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
BRG Down Counter
SSPxADD<6:0>
BRG Value
Baud Rate and Module
Interdependence
0Ch
18h
1Fh
63h
09h
27h
02h
09h
00h
F
OSC
/4
(2 Rollovers of BRG)
2
C Master mode at
DS39663F-page 225
312.5 kHz
400 kHz
100 kHz
400 kHz
308 kHz
100 kHz
333 kHz
100 kHz
1 MHz
F
SCL