PIC18F65J15T-I/PT Microchip Technology, PIC18F65J15T-I/PT Datasheet - Page 171

• Manufacturer Part Number: PIC18F65J15T-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J15T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18F65J15T-I/PT; PIC18F65J15T-I/PTTR

17.0
Members of the PIC18F87J10 family of devices all have
a total of five CCP (Capture/Compare/PWM) modules.
Two of these (CCP4 and CCP5) implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes and are discussed in this section. The other three
modules
standard Capture and Compare modes, as well as
Enhanced PWM modes. These are discussed in
Section 18.0
(ECCP) Module”.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-Bit Capture register, a 16-Bit
Compare register or a PWM Master/Slave Duty Cycle
REGISTER 17-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
U0
—
CAPTURE/COMPARE/PWM
(CCP) MODULES
(ECCP1,
“Enhanced
Unimplemented: Read as ‘0’
DCxB<1:0>: CCP Module x PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode; initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
1001 = Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
1011 = Reserved
11xx = PWM mode
U-0
—
ECCP2,
CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5)
is set)
is set)
reflects I/O state)
Capture/Compare/PWM
W = Writable bit
‘1’ = Bit is set
ECCP3)
DCxB1
R/W-0
implement
DCxB0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCPxM3
PIC18F87J10 FAMILY
R/W-0
register. For the sake of clarity, all CCP module opera-
tion in the following sections is described with respect
to CCP4, but is equally applicable to CCP5.
Capture and compare operations described in this
chapter apply to all standard and Enhanced CCP
modules. The operations of PWM mode, described in
Section 17.4 “PWM Mode”, apply to CCP4 and CCP5
only.
Note: Throughout this section and Section 18.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to register and bit names
that may be associated with a specific CCP
module are referred to generically by the use of
‘x’ or ‘y’ in place of the specific module number.
Thus, “CCPxCON” might refer to the control
register for ECCP1, ECCP2, ECCP3, CCP4 or
CCP5.
CCPxM2
R/W-0
x = Bit is unknown
CCPxM1
R/W-0
DS39663F-page 169
CCPxM0
R/W-0
bit 0