PIC16C770-I/P Microchip Technology, PIC16C770-I/P Datasheet - Page 214

• Manufacturer Part Number: PIC16C770-I/P
• Description: IC MCU CMOS A/D 2K 20MHZ 20-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of: RoHS Compliant
• Core: PIC
• Processor Series: PIC16C
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 256 B
• Data Rom Size: 256 B
• On-chip Adc: 6 bit
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: Through Hole
• Height: 3.3 mm
• Interface Type: I2C, SPI, SSP
• Length: 26.16 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C770I/P

PIC16C717/770/771
Prescaler, Timer2................................................................ 57
PRO MATE II Universal Device Programmer ................... 143
Program Counter
Program Memory .................................................................. 9
Program Verification.......................................................... 131
Programmable Brown-out Reset (PBOR) ................. 121, 122
Programming, Device Instructions .................................... 133
PWM (CCP Module)
PWM (ECCP Module) ......................................................... 56
Q
Q Clock ............................................................................... 57
R
R/W ..................................................................................... 66
R/W bit ................................................................................ 80
R/W bit ................................................................................ 78
R/W bit ................................................................................ 77
RAM. See Data Memory
RCE,Receive Enable bit, RCE ............................................ 69
RCREG ............................................................................... 13
RCSTA Register.................................................................. 13
Read/Write bit, R/W ............................................................ 66
Receive Overflow Indicator bit, SSPOV .............................. 67
REFCON ........................................................................... 102
Register File .......................................................................... 9
Register File Map ................................................................ 10
Registers
Reset......................................................................... 117, 121
Restart Condition Enabled bit, RSE .................................... 69
Revision History ................................................................ 207
RSE..................................................................................... 69
DS41120B-page 212
Select (T2CKPS Bits).................................................. 51
PCL Register............................................................... 22
PCLATH Register ............................................... 22, 128
Reset Conditions....................................................... 123
Interrupt Vector ............................................................. 9
Paging ..................................................................... 9, 22
Program Memory Map .................................................. 9
READ (PMR)............................................................... 43
Reset Vector ................................................................. 9
TMR2 to PR2 Match ................................................... 51
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 17
Block Diagram............................................................. 56
CCPR1H:CCPR1L Registers ...................................... 56
Duty Cycle................................................................... 57
Output Diagram........................................................... 57
Period.......................................................................... 56
TMR2 to PR2 Match ................................................... 56
FSR Summary ............................................................ 13
INDF Summary ........................................................... 13
INTCON Summary ...................................................... 13
PCL Summary............................................................. 13
PCLATH Summary ..................................................... 13
PORTB Summary ....................................................... 13
SSPSTAT............................................................ 66, 101
STATUS Summary ..................................................... 13
TMR0 Summary .......................................................... 13
TRISB Summary ......................................................... 13
Block Diagram........................................................... 121
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers ............................ 124
Reset Conditions for PCON Register........................ 123
Reset Conditions for Program Counter ..................... 123
Reset Conditions for STATUS Register .................... 123
WDT Reset. See Watchdog Timer (WDT)
S
S ......................................................................................... 66
SAE..................................................................................... 69
SCK .................................................................................... 70
SCL..................................................................................... 76
SDA .................................................................................... 76
SDI...................................................................................... 70
SDO .................................................................................... 70
Serial Data In, SDI .............................................................. 70
Serial Data Out, SDO ......................................................... 70
Slave Select Synchronization ............................................. 73
Slave Select, SS ................................................................. 70
SLEEP .............................................................. 117, 121, 130
SMP .................................................................................... 66
Software Simulator (MPLAB SIM) .................................... 142
SPE..................................................................................... 69
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 117
Special Function Registers ................................................. 11
Speed, Operating.................................................................. 1
SPI
SPI Clock Edge Select, CKE .............................................. 66
SPI Data Input Sample Phase Select, SMP ....................... 66
SPI Master/Slave Connection............................................. 71
SPI Module
SS ....................................................................................... 70
SSP..................................................................................... 65
SSP I
SSP Module
SSP Overflow Detect bit, SSPOV....................................... 77
SSPADD Register............................................................... 12
SSPBUF ................................................................. 13, 76, 77
SSPBUF Register ............................................................... 11
SSPCON............................................................................. 67
SSPCON Register .............................................................. 11
PIC16C717 ................................................................. 11
PIC16C717/770/771 ................................................... 11
PIC16C770 ................................................................. 11
PIC16C771 ................................................................. 11
Master Mode............................................................... 72
Serial Clock................................................................. 70
Serial Data In .............................................................. 70
Serial Data Out ........................................................... 70
Serial Peripheral Interface (SPI) ................................. 65
Slave Select................................................................ 70
SPI clock..................................................................... 72
SPI Mode .................................................................... 70
Master/Slave Connection............................................ 71
Slave Mode................................................................. 73
Slave Select Synchronization ..................................... 73
Slave Synch Timnig .................................................... 73
Block Diagram (SPI Mode) ......................................... 70
Enable (SSPIE Bit) ..................................................... 17
SPI Mode .................................................................... 70
SSPADD ..................................................................... 77
SSPBUF ............................................................... 72, 76
SSPCON .................................................................... 67
SSPCON2 ............................................................ 69, 70
SSPSR ................................................................. 72, 77
SSPSTAT ..................................................... 66, 76, 101
TMR2 Output for Clock Shift................................. 51, 52
SSP I
SPI Master Mode ........................................................ 72
SPI Master./Slave Connection.................................... 71
SPI Slave Mode .......................................................... 73
SSPCON1 Register .................................................... 76
2
C
2
C Operation ..................................................... 76
2002 Microchip Technology Inc.