ATMEGA16U2-MU Atmel, ATMEGA16U2-MU Datasheet - Page 200
ATMEGA16U2-MU
Manufacturer Part Number
ATMEGA16U2-MU
Description
MCU AVR 16K FLASH USB 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Core
AVR8
Processor Series
ATMEGA16x
Data Bus Width
8 bit
Maximum Clock Frequency
16 MHz
Data Ram Size
1.25 KB
Data Rom Size
512 B
Number Of Programmable I/os
22
Number Of Timers
2
Mounting Style
SMD/SMT
Height
0.95 mm
Interface Type
SPI, UART
Length
5 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
5 mm
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16U2-MU
Manufacturer:
RALINK
Quantity:
2 400
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21.8
21.9
7799D–AVR–11/10
Suspend, Wake-up and Resume
Detach
UADD contains the default address 00h after a power-up or an USB reset.
ADDEN is cleared by hardware:
When this bit is cleared, the default device address 00h is used.
After the USB line has been inactive for a period of 3 ms (J state), the controller set the SUSPI
flag and triggers the corresponding interrupt if enabled. The firmware may then set the FRZCLK
bit.
The CPU can also, depending on software architecture, disable the PLL and/or enter in the idle
mode to reduce the power consumption (especially in a bus powered application).
There are two ways to recover from the Suspend mode:
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WAKE-
UPI interrupt is triggered as soon as there are non-idle patterns on the data lines. Thus, the
WAKEUPI interrupt can occurs even if the controller is not in the “suspend” mode.
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is cleared
by hardware.
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared
by hardware.
The reset value of the DETACH bit is 1.
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit (the line
discharge time must be taken in account).
Figure 21-3. Detach a device in Full-speed:
• after a power-up reset,
• when an USB reset is received,
• or when the macro is disabled (USBE cleared)
1. Clear the FRZCLK bit. This is possible if the CPU is not in the Idle mode.
2. If the CPU is in idle mode, enable the WAKEUPI interrupt (WAKEUPE set). Then, as
• When the USB device controller is in full-speed mode, setting DETACH will disconnect the
pull-up on the D+. Then, clearing DETACH will connect the pull-up on the D+.
soon as an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered.
The firmware shall then clear the FRZCLK bit to restart the transfer.
UVREF
EN=1
D +
D -
Detach, then
Attach
ATmega8U2/16U2/32U2
UVREF
EN=1
D +
D -
200
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