AT90USB82-16MUR Atmel, AT90USB82-16MUR Datasheet - Page 212
AT90USB82-16MUR
Manufacturer Part Number
AT90USB82-16MUR
Description
MCU AVR USB 8K FLASH 32-QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB82-16MU.pdf
(307 pages)
Specifications of AT90USB82-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, PS/2, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-QFN
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, debugWIRE
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 212 of 307
- Download datasheet (4Mb)
20.18.2
212
AT90USB82/162
USB device endpoint registers
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - FNCERR -Frame Number CRC Error Flag
Set by hardware when a corrupted Frame Number in start of frame packet is received.
This bit and the SOFI interrupt are updated at the same time.
• 3-0 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - EPNUM2:0 Endpoint Number Bits
Set to select the number of the endpoint which shall be accessed by the CPU. See Section 20.5,
page 197 for more details.
Values greater than 100b are forbidden.
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4-0 - EPRST4:0 - Endpoint FIFO Reset Bits
Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or
when an USB bus reset has been received. See Section 20.3, page 196 for more information
Bit
Read/Wri
te
Initial
Value
Bit
Read/Wri
te
Initial
Value
Bit
Read/Wri
te
Initial
Value
7
-
R
0
7
-
R
0
7
-
R
0
6
-
R
0
6
-
R
0
6
-
R
0
5
-
R
0
5
-
R
0
5
-
R
0
4
FNCERR
R/W
0
4
-
R
0
4
EPRST D4
R/W
0
3
-
R
0
3
-
R
0
3
EPRST D3
R/W
0
2
-
R
0
2
EPNUM2:0
R/W
0
2
EPRST D2
R/W
0
1
-
R
0
1
R/W
0
1
EPRST D1
R/W
0
0
-
R
0
0
R/W
0
0
EPRST D0
R/W
0
7707F–AVR–11/10
UERST
UDMFN
UENUM
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