AT90USB82-16MUR Atmel, AT90USB82-16MUR Datasheet - Page 181
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AT90USB82-16MUR
Manufacturer Part Number
AT90USB82-16MUR
Description
MCU AVR USB 8K FLASH 32-QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB82-16MU.pdf
(307 pages)
Specifications of AT90USB82-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, PS/2, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-QFN
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, debugWIRE
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 181 of 307
- Download datasheet (4Mb)
18.6.4
Table 18-3.
18.6.5
18.7
7707F–AVR–11/10
UMSELn1
0
0
1
1
AVR USART MSPIM vs.
AVR SPI
USART MSPIM Control and Status Register n C - UCSRnC
USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
UMSELn Bits Settings
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in
Control and Status Register n C – UCSRnC” on page 167
USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The
UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is
enabled.
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for details.
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “USART Baud Rate Registers – UBRRLn and UBRRHn” on page 169.
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
Bit
Read/Write
Initial Value
• Master mode timing diagram.
• The UCPOLn bit functionality is identical to the SPI CPOL bit.
1
0
1
UMSELn0
0
7
UMSELn1
R/W
0
6
UMSELn0
R/W
0
Mode
Asynchronous USART
(Reserved)
Master SPI (MSPIM)
Synchronous USART
5
-
R
0
4
-
R
0
3
-
R
0
2
UDORDn
R/W
1
for full description of the normal
AT90USB82/162
1
UCPHAn
R/W
1
Table
18-3. See
0
UCPOLn
R/W
0
UCSRnC
“USART
181
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