AT90USB82-16MUR Atmel, AT90USB82-16MUR Datasheet - Page 210

• Manufacturer Part Number: AT90USB82-16MUR
• Description: MCU AVR USB 8K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB82-16MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

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AT90USB82/162
• 3 - EORSTI - End Of Reset Interrupt Flag
Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers
an USB interrupt if EORSTE is set.
Shall be cleared by software. Setting by software has no effect.
• 2 - SOFI - Start Of Frame Interrupt Flag
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1 ms).
This triggers an USB interrupt if SOFE is set..
• 1 - Reserved
• 0 - SUSPI - Suspend Interrupt Flag
Set by hardware when an USB “Suspend” ‘idle bus for 3 frame periods: a J state for 3 ms) is
detected. This triggers an USB interrupt if SUSPE is set.
Shall be cleared by software. Setting by software has no effect.
See Section 20.8, page 199 for more details.
The interrupt flags bits are set even if their corresponding ‘Enable’ bits is not set.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6 - UPRSME - Upstream Resume Interrupt Enable Bit
Set to enable the UPRSMI interrupt.
Clear to disable the UPRSMI interrupt.
• 5 - EORSME - End Of Resume Interrupt Enable Bit
Set to enable the EORSMI interrupt.
Clear to disable the EORSMI interrupt.
• 4 - WAKEUPE - Wake-up CPU Interrupt Enable Bit
Set to enable the WAKEUPI interrupt.
Clear to disable the WAKEUPI interrupt.
• 3 - EORSTE - End Of Reset Interrupt Enable Bit
Set to enable the EORSTI interrupt. This bit is set after a reset.
Clear to disable the EORSTI interrupt.
• 2 - SOFE - Start Of Frame Interrupt Enable Bit
Set to enable the SOFI interrupt.
Bit
Read/Wri
te
Initial
Value
7
-
R
0
6
UPRSME
R/W
0
5
EORSME
R/W
0
4
WAKEUPE
R/W
0
3
EORSTE
R/W
0
2
SOFE
R/W
0
1
-
R
0
0
SUSPE
R/W
0
7707F–AVR–11/10
UDIEN