AT90USB82-16MUR Atmel, AT90USB82-16MUR Datasheet - Page 183

• Manufacturer Part Number: AT90USB82-16MUR
• Description: MCU AVR USB 8K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB82-16MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19. USB controller
19.1
19.2
7707F–AVR–11/10
Features
Block Diagram
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•
•
The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-
ble port memory (DPRAM).
The USB controller requires a 48 MHz ±0.25% reference clock (for Full-speed compliance),
which is the output of an internal PLL. The PLL generates the internal high frequency (48 MHz)
clock for USB interface, the PLL input is generated from an external lower frequency (the crystal
oscillator or external clock input pin from XTAL1, to satisfy the USB frequency accuracy and jitter
; only this clock source allows proper functionnality of the USB controller).
The 48MHz clock is used to generate a 12 MHz Full-speed bit clock from the received USB dif-
ferential data and to transmit data according to full speed USB device tolerance. Clock recovery
is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with the jitter specifica-
tion of the USB bus.
To comply the USB Electrical characteristics, USB Pads (D+ or D-) should be powered within
the 3.0 to 3.6V range. As AT90USB82/162 can be powered up to 5.5V, the internal regulator
provides the USB pads power supply.
Support full-speed
Support ping-pong mode (dual bank), with transparent switch
176 bytes of DPRAM
– 1 endpoint of 64 bytes max, (default control endpoint)
– 2 endpoints of 64 bytes max, (one bank)
– 2 endpoints of 64 bytes max, (one or two banks)
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