PIC16F886-E/SP Microchip Technology, PIC16F886-E/SP Datasheet - Page 200

• Manufacturer Part Number: PIC16F886-E/SP
• Description: IC PIC MCU FLASH 8KX14 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F886-E/SP

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM164123 - KIT MANAGEMENT SYSTEM PICDEMDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F882/883/884/886/887
FIGURE 13-18:
13.4.12
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 13-19).
FIGURE 13-19:
DS41291D-page 198
BRG overflow,
Release SCL,
If SCL = 1, load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SDA
CLOCK ARBITRATION
Note: T
SCL
SDA
Falling edge of
9th clock
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
Write to SSPCON2
= one Baud Rate Generator period.
ACK
T
Set PEN
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low
T
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to set up Stop condition
BRG
Preliminary
T
SCL brought high after T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high
P
SCL = 1 for T
after SDA sampled high, P bit (SSPSTAT) is set
13.4.13
While in Sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
13.4.14
A Reset disables the MSSP module and terminates the
current transfer.
T
BRG
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
BRG
BRG
SLEEP OPERATION
EFFECT OF A RESET
, followed by SDA = 1 for T
T
BRG
SCL = 1, BRG starts counting
clock high interval
© 2007 Microchip Technology Inc.
2
C module can receive
OSC
BRG
*4),