ATMEGA8L-8MUR Atmel, ATMEGA8L-8MUR Datasheet - Page 111

• Manufacturer Part Number: ATMEGA8L-8MUR
• Description: MCU AVR 8KB FLASH 8MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Phase Correct PWM
Mode
2486Z–AVR–02/11
The extreme values for the OCR2 Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be
a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a
constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform
generated will have a maximum frequency of f
ture is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-
inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match
between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcount-
ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmet-
ric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the counter
reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one
timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2.
Figure 51. Phase Correct PWM Mode, Timing Diagram
TCNTn
OCn
OCn
Period
1
2
oc2
= f
clk_I/O
/2 when OCR2 is set to zero. This fea-
3
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
ATmega8(L)
(COMn1:0 = 2)
(COMn1:0 = 3)
Figure
111
51.