ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 94

• Manufacturer Part Number: ATTINY40-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 3X3 QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY40-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.10 Register Description
12.10.1
94
ATtiny40
TCCR1A – Timer/Counter1 Control Register A
• Bit 7 – TCW1: Timer/Counter1 Width
When this bit is written to one, 16-bit mode is selected as described
Timer/Counter1 width is set to 16-bits and the Output Compare Registers OCR1A and OCR1B
are combined to form one 16-bit Output Compare Register. Because the 16-bit registers
TCNT1H/L and OCR1B/A are accessed by the AVR CPU via the 8-bit data bus, special proce-
dures must be followed. These procedures are described in section
bit Mode” on page
• Bit 6 – ICEN1: Input Capture Mode Enable
When this bit is written to one, the Input Capture Mode is enabled.
• Bit 5 – ICNC1: Input Capture Noise Canceler
Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-
vated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four System Clock cycles when the noise canceler is enabled.
• Bit 4 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a cap-
ture is triggered according to the ICES1 setting, the counter value is copied into the Input
Capture Register. The event will also set the Input Capture Flag (ICF1), and this can be used to
cause an Input Capture Interrupt, if this interrupt is enabled.
• Bit 3 – CTC1: Waveform Generation Mode
This bit controls the counting sequence of the counter, the source for maximum (TOP) counter
value, see
Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see
ation” on page
• Bits 2:0 – CS1[2:0]: Clock Select1, Bits 2, 1, and 0
The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer1.
Table 12-4.
Bit
0x24
Read/Write
Initial Value
CS12
0
0
0
0
Figure 12-5 on page
CS11
0
0
1
1
Clock Select Bit Description
87).
TCW1
R/W
7
0
90.
CS10
0
1
0
1
ICEN1
R/W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
89. Modes of operation supported by the Timer/Counter unit are:
I/O
I/O
I/O
ICNC1
R/W
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
5
0
ICES1
R/W
4
0
CTC1
R/W
3
0
CS12
R/W
2
0
“Accessing Registers in 16-
CS11
Figure 12-5 on page
R/W
1
0
“Modes of Oper-
CS10
R/W
0
0
8263A–AVR–08/10
TCCR1A
89.